A full-chip RC parasitic extraction tool delivering Signoff-accurate extraction for ultra-large-scale digital, analog, SoC, and 3DIC heterogeneous integration. Supports multi-billion-gate parasitic netlist extraction, seamlessly integrating with mainstream backend platforms and Phlexing Signoff tools to deliver a one-stop solution. Provides precision modeling for advanced-node transistor structures and full-flow 3DIC extraction.

Employing the Random Walk algorithm to efficiently solve Maxwell's equations for parasitic extraction of complex 3D structures. With excellent parallel scalability, it is ideally suited for standard cells and IP blocks, particularly for critical-path parasitic analysis. Through precise modeling of Fin structures and other key device features, it effectively characterizes electrical properties of Pcells and standard cells.

The highest-accuracy Field Solver in the GloryEX family, based on the Finite Difference Method (FDM) to serve as the golden standard for parasitic extraction. Performs high-fidelity 3D modeling based on foundry silicon data and process rules, incorporating BEOL, CMP, and Etch-Loading process effect modules to deliver simulation results closely matching actual manufacturing.

A silicon-proven, high-accuracy EM and IR Drop analysis tool meeting industry golden standards. Supports multi-billion-instance designs with full-chip Signoff EMIR analysis covering power grid integrity, signal wire reliability, and voltage drop. Supports 2.5D/3D stacked die configurations with Hybrid Bonding and Micro Bump technologies.

A chip-level multi-physics analysis tool integrating power and thermal simulation. Incorporates a Signoff-grade power analysis engine for accurate average and peak power calculation, with generated power results serving as input for thermal simulation. Embeds a specialized mesh partitioning engine and high-performance solver for chip thermal analysis, with unique power modeling technology supporting power recalculation based on temperature, voltage, and frequency.

Integrates a Signoff-grade power analysis engine that precisely calculates average and peak power based on design netlists, standard cell libraries, parasitic parameters, and vector waveforms. Effectively assists users in power verification, pinpointing power hotspots, and troubleshooting power anomalies. Supports dynamic power calculation and RTL waveform-based power analysis across advanced process nodes.

A high-precision STA platform integrating static timing analysis, signal integrity, and power analysis. Features innovative variation-aware modeling with dual NLDM/CCS timing models and industry-leading silicon correlation. Through intelligent multi-core parallel compute engines, it efficiently handles ultra-large designs with both flat and hierarchical methodologies.