Characterization of Standard Cell and SRAM.
Parasitic capacitance extraction of critical paths.
Precise extraction of Self-coupling capacitance and Distributed capacitance.
High potential for parallel and hierarchical computing. Parallel computing with several thousand CPUs.
Output after-reduction and smallest possible netlist for designers’ reference.
Low memory consumption.
Technology modeling for complex geometries and complicated processing effects.
High-precision modeling and parasitic extraction of BEOL, MEOL, and FEOL processing in planar MOS and FinFET manufacturing.
Precision level matching with Foundries’ Golden data.
Precision verification from multiple foundries.
Seamless integration with major digital Back-end flows.
Easy to use 3D GUI – GxViewer for viewing details of technology nodes.
3D viewing interface for device structures, allowing developers to check detailed processing data and 3D structures of modelling. Highly-accurate characterization of conductors and dielectric parameters.
Encrypted techfile, ensuring information security of the foundry.
GloryEX3D
Device-Level High-Efficiency Parasitic Field Solver
Overview
Based on Radom Walk method, GloryEX3D obtains approximate solutions of partial differential equations of Maxwell functions. This field solver can be applied for solving complex structures in a convenient manner. Also, GloryEX3D can be readily used for parallel computing and applied in solving parasitic RC of standard cells and IP. GloryEX3D can also calculate parasitic of the critical paths in advanced IC.
GloryEX3D ensures the precision requirements for every critical point and every critical parameter. GloryEX3D can be applied in designs of advanced process nodes and planar MOS. With its industry leading solving efficiency and capacity for parallel computing, GloryEX3D can process calculation in a fast manner and renders highly precise results that meet parasitic modeling requirements from foundries. Through detailed modeling of device characteristics including Fin number, M0 (local interconnects), M1 and V0 features of P-cells and Template Cells are characterized. GloryEX3D can be applied in high-precision extraction of small to middle sized layouts or high-precision extraction of critical paths in chips. All extractions meet the Signoff level precision requirement.
Highlights
Demonstration
Products
GloryEXChip-Level RC Parasitic Extraction Tool
GloryEX3DDevice-Level High-Efficiency Parasitic Field Solver
GloryPolarisHigh-Precision 3D Modeling Tool for Parasitic Parameters
GloryBoltFull-Chip Power Grid/Signal Line EM/IR Signoff Tool
PhyBoltMulti-Physics Domain-Coupling Analysis for 3D IC and Chiplet
GloryWattFull-chip Power Signoff Tool
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