GloryBolt is a silicon-proven, high-accuracy power grid electromigration (EM), signal line EM, and IR drop (EMIR) analysis tool meeting industry golden standards. Supporting multi-billion-instance ultra-large-scale designs, GloryBolt delivers full-chip signoff-accurate EMIR analysis covering power grid integrity, signal wire reliability, current density, and voltage drop. The tool supports 2.5D and 3D arbitrary stacked die configurations with hybrid bonding, micro bump, and other bonding technologies. Its unique elastic compute architecture provides massive capacity to tackle the challenges of ultra-large-scale IC designs. GloryBolt has received official certification from multiple mainstream foundries and is qualified for production-grade design flows. The tool comprehensively covers Static IR, Dynamic IR, Signal EM, PG EM, and Grid Check analysis, with integrated OpenShort detection, ESD analysis, package co-analysis, and GDS-to-LEF/DEF format conversion. GloryBolt also provides chip-level CPM and CTM models for system-level power integrity co-analysis.
High-Precision Simulation:
GloryBolt Dynamic IR Drop analysis supports GPL (GloryBolt Power Library), a proprietary library generated by GloryBolt that provides more accurate cell current waveform compared to traditional .lib files, significantly improving dynamic IR drop analysis precision and more realistically reflecting actual chip operating conditions.
High-Performance Architecture:
GloryBolt's DMP (Distributed Machine Processing) architecture enables parallel execution of multiple simulation tasks, dramatically reducing memory consumption and runtime. Performance scales linearly with compute resources. Physical partition methodology ensures correct boundary conditions during matrix solving, delivering performance improvements while maintaining Signoff accuracy.
Multi-Die Heterogeneous Integration Support:
Supports full-chip power grid and signal line simulation for advanced packaging systems. Accommodates 2.5D and 3D arbitrary stacked die configurations with hybrid bonding, micro bump, and other bonding technologies. Provides a unified, high-precision, high-capacity reliability analysis flow for multi-die heterogeneous integration.
Multi-Process Node Certification:
Silicon-validated at leading domestic foundries across multiple advanced process nodes including 28nm, 14nm and below. Process files and GPL databases have been successfully deployed in multiple customer design flows and tapeout projects.
Full-Chain EMIR Analysis:
Supports package-die co-simulation with RCLK and other Spice-format package netlists, including PCB Model integration, enabling system-level Die-Package-PCB EMIR analysis.
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