GloryEye is a high-precision Static Timing Analysis (STA) platform integrating static timing analysis, signal integrity analysis, and power analysis. With comprehensive design constraint parsing capabilities and industry-leading silicon data correlation, GloryEye features an innovative variation-aware modeling and computation architecture, supporting both NLDM and CCS dual timing models. Through intelligent multi-core parallel compute engines and optimized memory management, GloryEye efficiently handles ultra-large designs while supporting both flat and hierarchical analysis methodologies, providing complete timing verification from RTL to GDSII to help design teams achieve faster timing closure.
· 3DIC Static Timing Analysis:
Full support for 3DIC structure parasitic parameter extraction and back-annotation, combined with advanced hierarchical Signoff flows to efficiently address timing verification challenges for large-scale chip designs.
· Multi-Mode Multi-Corner Parallel Analysis:
Distributed multi-scenario engine supporting concurrent multi-voltage, multi-mode, multi-corner (MMMC) timing verification through intelligent scheduling with multi-threaded optimization. Delivers flexible analysis capabilities from block-level to full-chip, significantly improving verification efficiency.
· Distributed Timing Signoff Analysis:
Partitionable timing Signoff solution for ultra-large designs, supporting decomposition of the full design into independent Signoff tasks processed in parallel. Highly automated flow significantly reduces manual intervention and accelerates design iteration cycles.
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