GloryEX is a full-chip RC parasitic extraction solution delivering Signoff-accurate parasitic extraction for ultra-large-scale digital chips, analog designs, SoCs, and 3DIC heterogeneous integration. For SoC designs, GloryEX supports gate-level parasitic netlist extraction for multi-billion-gate integrated circuits and integrates seamlessly with mainstream backend design platforms.It also interfaces smoothly with other Phlexing Signoff tools to deliver a one-stop Signoff solution. For analog applications, GloryEX accepts LVS databases from third-party tools as input, leveraging the GloryEX3D compute engine to deliver precision modeling of advanced-node transistor structures, meeting the stringent accuracy requirements for transistor-level parasitic netlist extraction. In 3DIC heterogeneous integration applications, GloryEX supports arbitrary stacking configurations with cross-die coupling capacitance extraction, TSV equivalent modeling, and full-flow adaptation for heterogeneous integration. The tool pioneers unified high-precision modeling for both 2D and 3D structures, enabling sequential 3D verification, transistor-level verification, and gate-level verification to ensure data integrity across all design scenarios.
· Massively Parallel Extraction:
Supports adaptive automated partitioning with a massively parallel extraction architecture, enabling parasitic extraction for multi-billion-gate designs with dramatically improved throughput and scalability.
· Multi-Corner Parallel Extraction:
Supports Multi-Corner Parallel Extraction (MCPE), achieving full-chip parasitic parameter extraction efficiency improvements of over 35%.
· Virtual Metal Fill Assessment:
Built-in Virtual Metal Fill (VMF) capability enables accurate quantification of metal fill impact on parasitic capacitance without requiring separate fill operations, significantly reducing iteration optimization turnaround time.
· 3DIC Cross-Foundry Data Fusion:
Compatible with mainstream foundry 3DIC Bonding GTF formats, enabling seamless multi-foundry CAPTAB database integration and breaking cross-foundry collaboration data interoperability barriers.
· Signoff-Accurate Full-Flow Guarantee:
Deep integration with GloryPolaris and GloryEX3D field solvers, supporting PDK accuracy verification closure from Silicon Data characterization through device-level parasitic modeling, interconnect modeling, foundation IP characterization, to full-chip parasitic extraction—ensuring data reliability across all design scenarios.
· One-Stop Signoff Flow:
Seamlessly integrates with GloryEye static timing analysis, GloryBolt power grid/signal EMIR Signoff, and PhyBolt multi-physics coupled analysis tools within the Phlexing Signoff platform, delivering a one-stop Signoff solution.
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