GloryEX, Phlexing’s chip-level RC parasitic extraction tool, provides high-performance extraction solutions for diverse design scenarios including digital, analog, SoC and etc. Its precision level meets the criteria of Signoff flow. In SoC design, GloryEX performs Gate-level RC extraction for over-100-million instance large-scale integrated circuits. GloryEX’s flow seamlessly integrates with major digital back-end flows and cooperates in a perfect way with other Phlexing’s Signoff tools, including EM/IR, Timing, Power and etc. Together, GloryEX and other Phlexing’s tools offer an all-inclusive Signoff solution. In analog design application, GloryEX can take in LVS data from third-party tools as input. Combined with calculation engine in GloryEX3D, GloryEX conducts high-precision modeling of transistor structures of advanced process nodes to perform highly precise transistor-level parasitic extraction. All extraction results can be loaded into third-party layout platforms to help users manage the design flow in an easy way. Aiming at different process nodes, GloryEX has timely and accurately adopted modeling for different process effects including optical proximity correction (OPC), chemical mechanical processing (CMP), low-k damage, double/multiple patterning and etc. GloryEX’s calculation precision has received verification from top foundries and has been proved by multiple Tape-Outs.