GloryEX, Phlexing’s chip-level RC parasitic extraction tool, provides high-performance extraction solutions for diverse design scenarios including digital, analog, SoC and etc. Its precision level meets the criteria of Signoff flow. In SoC design, GloryEX performs Gate-level RC extraction for over-100-million instance large-scale integrated circuits. GloryEX’s flow seamlessly integrates with major digital back-end flows and cooperates in a perfect way with other Phlexing’s Signoff tools, including EM/IR, Timing, Power and etc. Together, GloryEX and other Phlexing’s tools offer an all-inclusive Signoff solution. In analog design application, GloryEX can take in LVS data from third-party tools as input. Combined with calculation engine in GloryEX3D, GloryEX conducts high-precision modeling of transistor structures of advanced process nodes to perform highly precise transistor-level parasitic extraction. All extraction results can be loaded into third-party layout platforms to help users manage the design flow in an easy way. Aiming at different process nodes, GloryEX has timely and accurately adopted modeling for different process effects including optical proximity correction (OPC), chemical mechanical processing (CMP), low-k damage, double/multiple patterning and etc. GloryEX’s calculation precision has received verification from top foundries and has been proved by multiple Tape-Outs.

Based on Radom Walk method, GloryEX3D obtains approximate solutions of partial differential equations of Maxwell functions. This field solver can be applied for solving complex structures in a convenient manner. Also, GloryEX3D can be readily used for parallel computing and applied in solving parasitic RC of standard cells and IP. GloryEX3D can also calculate parasitic of the critical paths in advanced IC. GloryEX3D ensures the precision requirements for every critical point and every critical parameter. GloryEX3D can be applied in designs of advanced process nodes and planar MOS. With its industry leading solving efficiency and capacity for parallel computing, GloryEX3D can process calculation in a fast manner and renders highly precise results that meet parasitic modeling requirements from foundries. Through detailed modeling of device characteristics including Fin number, M0 (local interconnects), M1 and V0 features of P-cells and Template Cells are characterized. GloryEX3D can be applied in high-precision extraction of small to middle sized layouts or high-precision extraction of critical paths in chips. All extractions meet the Signoff level precision requirement.

Based on Finite Difference Method, GloryPolaris calculates partial differential equations of Maxwell functions. GloryPolaris is applicable for mini-scope, very-high precision calculations such as RC extractions of general structures of the metal interconnect model. Because of its definitive nature, GloryPolaris provides results of highest precision – the Golden standard. GloryPolaris provides parasitic extractions of highest precision for FinFET and Planar MOS. Given data including silicon data, pattern, rule, and profile from Foundry’s TD Department, GloryPolaris completes highest-precision 3D modeling. GloryPolaris takes into account of processing effects including BEOL, CMP, etch-loading, and TSV modeling. GloryPolaris can be applied in the exact calculation of device-level parasitic capacitances and in building up metal interconnect models.

GloryBolt is a high-precision, high-efficiency IR drop and EM (Electromigration) analysis tool that reaches the industry’s golden standard and verified by silicon data. GloryBolt offers full-chip reliability analysis of power grid and signal line. It can be used in super IC design of 100s million instances. GloryBolt offers full-chip Signoff precision analysis of power, current density, IR drop, Electromigration and reliability. With usability and user-friendly operation flows, GloryBolt helps users obtain analysis data for Signoff in a fast manner. Combined with diagnosis results presented in a detailed GUI, GloryBolt can guide users to precisely locate design weakness, evaluate chip’s design in a holistic manner and expedite efficiency of design iterations. The Signoff precision of GloryBolt has received recognition and verification of every major foundry. GloryBolt offers complete solutions for Static IR, Dynamic IR, PG EM, Signal EM, Grid Check. Entitled with its unique elastic computing structure, GloryBolt offers great capacity to conquer challenges brought by large-scale IC designs.

PhyBolt provides a complete power and thermal coupling solution for chip integration and packaging, with its built-in solvers capable of simulating electron conducting behaviors accurately. PhyBolt supports user-defined parameters settings, and provides optimized input set based on accuracy requirements and computing capacity. Embedded with a pool of thermal models, PhyBolt supports different formats of CAD files and GDS files inputs. PhyBolt equips with Signoff accuracy power computing modes, allowing seamless integration with power-thermal simulation. Its power computing adjusts to on-chip thermal levels to improve simulation accuracy. PhyBolt’s power-thermal conductivity models allow users to quickly assess chips’ power-thermal conditions under different voltage, frequency and process corners.

GloryWatt offers signoff-precision level power analysis engine. After reading in design netlist, liberty, waveform files, GloryWatt can precisely calculate the design’s average and peak power under given scenarios. This helps designers verify design’s power, locate power violations and fix bugs.