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GloryET®
Signoff-Closure ECO Tool

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GloryET®

GloryET is a signoff-closure ECO tool—the signoff-closure core of the τ-Aware ToolFramework. It completes one-stop repair and optimization of timing, power, area, reliability, and other violations at the signoff stage, powered by a fully self-owned, signoff-level timing engine and a high-performance ECO optimization engine.

Key Features

Supports closed-loop detection and optimization of all violation types: Setup, hold, DRV, power, area, and more.
Supports parallel repair of timing violations across all scenarios.
Includes a complete pessimism-reduction technology stack: AOCV, POCV, and PBA.
Supports three accuracy models: Logic-Only, Total RC, and SPEF.
Supports dual GBA/PBA repair modes.
Physically aware congestion prediction: Deeply fuses physical placement and routing information to predict the congestion impact of modifications.
Compatible with Linux and ARM platforms.

Products Highlights

01

High-accuracy timing engine ensures final signoff without regression
Powered by a fully self-developed, high-precision, signoff-level timing engine that is highly aligned with the industry golden standard in SPEF mode; the underlying core algorithms and data models are fully self-owned IP; supports GBA/PBA dual analysis modes.

02

High-performance parallel ECO engine
Supports MMMC multi-scenario parallel repair; maintains outstanding computing efficiency on giga-scale designs with hundreds of millions of instances, dramatically compressing back-end iteration cycles.

03

Complete MMMC/OCV/PBA support reduces pessimism
Built-in AOCV, POCV, and PBA pessimism-reduction technologies; supports parallel repair of timing violations across all scenarios.

04

Automatic repair of all violation types
Supports automatic detection and optimization closed loops for setup, hold, DRV, power, area, IR drop, and other violation scenarios—compressing manual iterations from weeks to days.

05

τ-Aware cross-tier timing ECO
Reuses the same signoff-level timing engine as GloryEye at the underlying layer, fully supporting cross-tier timing-violation repair in 3D stacked scenarios, with repair accuracy highly aligned to final signoff.

Applications

Application Scenarios

Signoff-closure stage of digital SoC designs such as MCUs, IPCs, and AI compute chips. For giga-scale designs with hundreds of millions of instances, it is used for batch repair and optimization of timing, power, reliability, and other violations before tape-out. Adapts to 14nm, 10nm, and 7nm advanced FinFET processes and 2.5D/3DIC heterogeneous integration.

Anchored in Advanced-Node Signoff ,Empowering aτ-Aware EDA Framework

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