GloryEX®
GloryEX is a full-chip RC parasitic extraction tool—the accuracy foundation (τ-precision baseline) of the τ-Aware ToolFramework. Targeting ultra-large-scale digital chips, analog chips, SoCs, and 3DIC heterogeneous integration, it delivers a high-performance, signoff-level full-chip RC parasitic extraction solution. It supports parasitic netlist extraction for multi-billion-gate integrated circuits and pioneers unified high-precision modeling for both 2D and 3D structures.
Key Features
Complex-geometry and process-effect modeling for 65nm down to 10nm-and-below nodes (including FinFET): Covers OPC, CMP, low-k damage, and double/multiple patterning effects; accuracy certified by leading foundries in China and abroad and validated through silicon tape-outs.
Device-level accuracy loop: Works with GloryEX3D to model FinFET device parasitics and generate CAPTAB, enabling efficient, high-accuracy parasitic extraction at 14nm and below; supports LEF, DEF, CCI, and other mainstream data formats.
Full-stack 3DIC heterogeneous-integration parasitic modeling: Supports VIX coupling-capacitance extraction and multi-die netlist merging for arbitrary stacking configurations; supports TSV RC/RCL subcircuit modeling and TSV-to-TSV substrate RSUB/CSUB/CEFF equivalent modeling, with a built-in field solver for precise TSV-to-substrate parasitic capacitance calculation.
Extracted view in mainstream design platforms: Back-annotates parasitic into the graphical design environment, making it easy for users to analyze and further optimize designs.
Graphical debugger interface:Provides LVS layer information together with parasitic capacitance and resistance data, facilitating analysis of input data and extraction results.
Products Highlights
Applications
Application Scenarios
SoC, ASIC, memory, custom, AMS, and 3DIC heterogeneous packaging across multiple design scenarios. Supports 65nm down to 10nm-and-below process nodes (including FinFET); accuracy certified by leading foundries in China and abroad.