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    GloryBolt®
    Full-Chip Power Grid and Signal EMIR Signoff Tool

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    HomeProducts & ServicesProductsGloryBolt®

    GloryBolt®

    GloryBolt is a full-chip power/signal reliability signoff tool—the reliability-signoff core of chip signoff within the τ-Aware tool framework. Meeting industry golden standards, it supports ultra-large-scale designs with tens of billions of instances and provides signoff-level power, current-density, voltage-drop, electromigration (EM), and reliability analysis across the full chip.

    Key Features

    Static IR Drop: Vector, vectorless, mix-mode, and back-annotated-power static voltage-drop analysis.
    Dynamic IR Drop: Vector, vectorless, mix-mode, and back-annotated-power dynamic voltage-drop analysis.
    Power EM: Electromigration analysis on power networks in AVG mode.
    Signal EM: Electromigration analysis on signal lines in AVG, PEAK, and RMS modes.
    Grid Check: Equivalent-resistance and shortest-path-resistance analysis, 30× faster than traditional algorithms.
    Chip-Package Analysis: Supports package analysis with package parasitic parameters.
    Chip Power Model: Supports extraction of power equivalent models.
    ESD: Supports ESD analysis in B2B, B2C, and other modes.
    VCD Checker: Reads DEF, SPEF, timing, and library files to analyze waveform quality.
    Open/Short Analysis:Outputs reports of unconnected instances, wires, vias, and shorted segments.

    Products Highlights

    01

    High-Accuracy Simulation
    Dynamic IR-drop analysis supports GPL (GloryBolt Power Library), providing more accurate cell current waveforms than traditional library files and significantly improving dynamic IR-drop accuracy.

    02

    High-Performance Elastic Architecture
    The DMP scheme runs simulation tasks in parallel with performance scaling linearly with compute resources; physical partitioning ensures correct boundary conditions during matrix solving, enabling "true" 3D analysis.

    03

    Multi-Dimensional Heterogeneous-Integration Support
    Supports 2.5D and 3D stacking in arbitrary configurations, as well as hybrid bonding, micro-bumps, and other bonding forms.

    04

    Silicon-Validated at Multiple Process Nodes
    Rigorously silicon-validated at 28nm, 14nm, and more advanced nodes at leading Chinese foundries.

    05

    Full-Chain EMIR Analysis
    Supports package-die co-simulation and Spice-format package netlists with RCLK and other parameters, as well as package netlists with PCB models, enabling die-package-PCB system-level EMIR analysis.

    06

    τ-Aware Electro-Thermal Coupling Loop
    Based on the accurate multi-die temperature distributions from PhyBolt, it enables thermal-aware EM analysis, breaking through the traditional single-temperature assumption.

    Applications

    Application Scenarios

    Power and signal reliability signoff for large-scale digital chips such as SoCs and AI chips. Supports multi-billion-instance scales under 2.5D/3D stacking in arbitrary configurations. Within the τ-Aware design flow, it performs thermal-aware EM analysis based on PhyBolt temperature data, delivering true reliability signoff for 2.5D/3DIC/chiplets.

    Anchored in Advanced-Node Signoff
    Empowering a τ-Aware EDA Framework

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