GloryEye®
GloryEye is a full-chip static timing analysis tool—the timing-signoff core of chip signoff within the τ-Aware ToolFramework. It integrates static timing analysis, signal-integrity analysis, and power analysis in one platform and supports both NLDM and CCS timing models. It efficiently handles designs exceeding 100M instances in flat (flattened) mode and 500M instances in hierarchical mode.
Key Features
Timing checks: Supports setup, hold, recovery, and other timing-check configurations, covering all scenario verification needs.
Timing constraints:Supports definition and parsing of mainstream timing constraints including clocks, input delay, and output delay.
GBA/PBA dual analysis modes: Supports graph-based analysis (GBA) and path-based analysis (PBA), with PBA offering both Path and Exhaustive modes to effectively reduce timing pessimism.
NLDM/CCS dual models: Compatible with both NLDM and CCS timing models, fully covering 7nm-and-below advanced processes and traditional mature processes.
Variation analysis: Supports the three major on-chip variation models—GOCV, AOCV, and POCV—adapting from mature processes down to 14nm-and-below advanced nodes.
SI analysis: Integrates signal-integrity analysis, supporting crosstalk-delay and glitch analysis.
CRPR:removes timing pessimism caused by double-counting of clock paths, further improving analysis accuracy.
Hierarchical STA flow: Supports hierarchical (block-level) timing signoff flows. (Source: "Hyperscale STA Flow" — see note in Chapter 10.)
Distributed multi-scenario analysis: Supports concurrent analysis across combinations of multiple frequencies, voltages, and process corners.
Multi-voltage-domain analysis: Adapts to low-power designs; supports multi-voltage-domain timing analysis including level-shifter timing checks.
3DIC timing analysis: Supports 2.5D/3D stacked-chip timing analysis, accounting for the timing impact of vertical interconnect structures.
SPICE-class high-accuracy engine: Self-developed RC computation engine, leveraging accurate parasitics and process libraries to achieve near-SPICE simulation accuracy.
Integrated power and timing analysis: Integrates static and dynamic power analysis, enabling combined timing-and-power signoff.
TWF file export: Supports exporting timing-window (TWF) files for IR-drop, dynamic-power, and electromigration analysis in PI tools.
Products Highlights
Applications
Application Scenarios
Gate-level timing signoff for large-scale digital chips (CPU, GPU, MCU, etc.). Supports design scales of 100M+ instances in flat mode and 500M+ instances in hierarchical mode.