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GloryGrid®
Early Power-Grid Assessment and Optimization Tool

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GloryGrid®

GloryGrid is an early power-grid assessment and optimization tool—the core component for power distribution within the τ-Aware ToolFramework. Facing the rising complexity of power-delivery design under the new scaling paradigm, GloryGrid moves power-network planning left into the early stages of chip design, covering the pre-placement through pre-PG-route stages.

Key Features

Automatically generates power-network patterns for 2D/2.5D/3D architectures based on user constraints.
Supports static and dynamic IR-drop analysis, PG EM analysis, and shortest-path-resistance analysis to quantify and evaluate power-scheme robustness.
Supports open/short checking of power networks to quickly locate connectivity violations.
Supports three flexible flows for building power schemes: Config, DEF, and Hybrid.
Supports multi-task concurrent simulation.
Supports ultra-large-scale designs with billions of instances.
Supports 2.5D/3DIC and chiplet heterogeneous integration.
Supports disturbance analysis of key interconnect structures—TSVs, hybrid bonding, and upper-level signal routing—on cross-die power-delivery quality.

Products Highlights

01

Native support for 3DIC/Chiplet heterogeneous integration
Natively builds arbitrary TSV/hybrid bonding stacking configurations and accurately analyzes the microscopic disturbance of vertical interconnect structures on global power-delivery quality, ensuring power consistency across the heterogeneous system.

02

Automatic PG pattern generation with early-stage, signoff-level EMIR analysis
Requires only the tech file and TLEF to automatically generate a power network and perform EMIR analysis; supports static/dynamic IR drop and PG EM analysis, plus shortest-path-resistance analysis to quantify power-scheme robustness.

03

Multi-mode flow-adaptation engine
Supports Config, DEF, and Hybrid flows to flexibly build power schemes, meeting needs from top-level architectural conception through the Pre-PG-Route stage.

04

Distributed parallel acceleration engine
Adopts DMP parallel-solver technology, supports multi-task concurrent simulation, and handles ultra-large-scale designs with billions of instances.

05

Interactive visual diagnosis interface
Intuitively presents PG-network topology, IR-drop heat-maps, and EMIR violations, enabling one-click root-cause location of design defects; supports open/short checking to quickly locate connectivity violations.

Applications

Application Scenarios

Early PDN planning and EMIR risk assessment for ultra-large-scale chips with demanding scaling requirements. For 2.5D/3DIC and Chiplet heterogeneous integration, it addresses disturbance analysis of key interconnect structures—TSVs, hybrid bonding, and upper-level signal routing—on cross-die power-delivery quality.

Anchored in Advanced-Node Signoff ,Empowering aτ-Aware EDA Framework

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