Abstracts intermediate computation results into parameterized models, supporting dynamic power recalculation based on temperature, voltage, and frequency—greatly improving iteration and co-simulation efficiency.

Fully supports low-power design flows and UPF, provides wire-load models for fast post-synthesis power evaluation; the built-in toggle-rate propagation algorithm enables power estimation directly from RTL waveforms with error within 3% against full-netlist simulation.

Supports interpolation-based power calculation at arbitrary voltage/temperature points; supports automatic name matching between RTL VCD and gate-level netlists.

Fully supports standard back-end design formats—DEF, Verilog, Liberty, SPEF, VCD, and SAIF—for seamless integration with back-end design flows.

Supports independent fine-grained hierarchical power modeling with spatial-distribution output; provides both steady-state average-power and transient time-based power data as heat sources, respectively suited to steady-state thermal analysis and dynamic thermal simulation; power results flow seamlessly into the electro-thermal coupling flow, supporting thermal-aware timing signoff through the "power–thermal–timing" multi-physics transmission chain.