Choose language
Back

Products

PhyBolt®
Chip-Level Multi-Physics Analysis Tool

Download

PhyBolt®

PhyBolt® is a chip-level multi-physics analysis tool—the multi-physics coupling engine at the front-end architecture stage of the τ-Aware ToolFramework. Grounded in advanced processes, it realizes coupled analysis of power, thermal, and reliability effects across multiple physical domains. It builds fast full-module power-thermal simulation models and pre-allocates energy budgets, providing physical-feasibility evidence for architecture decisions.

Key Features

Embeds a signoff-level power analysis engine, supporting full-chip average/peak power calculation.
Integrates a power-temperature co-simulation flow with temperature back-annotation and dynamic adjustment, realizing closed-loop τ-Aware electro-thermal optimization.
Supports standard back-end design formats including DEF, Verilog, Liberty, SPEF, VCD, and SAIF for seamless design-flow integration.
Supports low-power design with wire-load models and toggle-rate propagation algorithms, aiding post-synthesis power estimation and optimization.
Supports steady-state and transient thermal analysis.
Supports thermal model order reduction: parameter count is reduced by five orders of magnitude with temperature error within 1°C.
Supports package- and board-level Joule-heating analysis; through electro-thermal co-analysis, accurately captures on-chip and package temperature distributions.
Works with GloryBolt to enable thermal-aware electromigration analysis, providing accurate multi-die temperature distributions for EM analysis.
Provides a flexible Python interface supporting DVFS and other dynamic regulation-algorithm simulations to meet diverse simulation needs.

Products Highlights

01

Unique power modeling technology
100×+ speedup
Abstracts intermediate power-computation results into efficient mathematical models; substituting arbitrary V/T/F values enables rapid power evaluation, with computation speed more than two orders of magnitude faster than full simulation.

02

Fast thermal simulation for advanced packaging
10–30× performance gain
A mesh-partitioning engine and high-performance solver purpose-built for chip thermal analysis provide high-accuracy equivalent modeling of heterogeneous media such as TSVs, micro-bumps, and hybrid bonding; the customized simulation engine delivers 10–30× higher performance than traditional methods.

03

Thermal model order reduction — five orders of magnitude fewer parameters
Reduces the thermal-model parameter count by five orders of magnitude while keeping temperature error within 1°C.

04

τ-Aware electro-thermal coupling loop
Integrates the power-temperature co-simulation flow with temperature back-annotation and dynamic adjustment; jointly enables thermal-aware EM analysis with GloryBolt, providing accurate inter-die temperature-coupling results.

05

Package- and board-level Joule-heating analysis
Incorporates electro-thermal coupling effects between chip and package into the analysis, delivering accurate on-chip and package temperature distributions with multi-scale thermal analysis.

06

Flexible Python interface and low-power support
Provides unified command interfaces compliant with Python syntax, supporting DVFS and other dynamic-regulation algorithm simulations; fully supports low-power design flows with wire-load models and toggle-rate propagation algorithms.

07

τ-Aware collaboration
Provides GloryBolt with accurate multidie temperature distributions (Chip Thermal Model (CTM)) for thermalaware electromigration (EM) analysis; provides power-thermal coupling data as input for GloryGrid early PDN planning; and provides temperature back-annotation data to GloryWatt, realizing a dynamic power-thermal closed loop.

Applications

Application Scenarios

System power evaluation under arbitrary packaging forms and operating modes; power-thermal coupling analysis; on-chip temperature-gradient analysis; multi-die temperature-coupling analysis for 2.5D/3DIC/Chiplets; thermal-feasibility analysis of advanced packaging systems; floor-plan and temperature-sensor placement optimization.

Anchored in Advanced-Node Signoff ,Empowering aτ-Aware EDA Framework

Please provide your contact information

By providing your information, you agree to our processing of your personal data in order to
carry out the activity and related communications. For details, please refer to the Privacy Policy.

Submit