Embeds a signoff-level power analysis engine, supporting full-chip average/peak power calculation.
Integrates a power-temperature co-simulation flow with temperature back-annotation and dynamic adjustment, realizing closed-loop τ-Aware electro-thermal optimization.
Supports standard back-end design formats including DEF, Verilog, Liberty, SPEF, VCD, and SAIF for seamless design-flow integration.
Supports low-power design with wire-load models and toggle-rate propagation algorithms, aiding post-synthesis power estimation and optimization.
Supports steady-state and transient thermal analysis.
Supports thermal model order reduction: parameter count is reduced by five orders of magnitude with temperature error within 1°C.
Supports package- and board-level Joule-heating analysis; through electro-thermal co-analysis, accurately captures on-chip and package temperature distributions.
Works with GloryBolt to enable thermal-aware electromigration analysis, providing accurate multi-die temperature distributions for EM analysis.
Provides a flexible Python interface supporting DVFS and other dynamic regulation-algorithm simulations to meet diverse simulation needs.