GloryEye|PHLEXING

GloryEye

Full-Chip Static Timing Analysis Tool

Overview

GloryEye is a cutting-edge Static Timing Analysis (STA) tool for digital integrated circuits. It meets critical requirements for maximum correlation with foundry silicon data while ensuring high efficiency, delivering reasonable runtime and high capacity for comprehensive analysis of designs at any scale. GloryEye provides precise timing constraints and optimized margins to guarantee functional correctness while minimizing timing pessimism. Leveraging variation-aware modeling and computation, it supports Nonlinear Delay Models (NLDM) and Composite Current Source (CCS) models. It enables rapid multi-core processing with limited memory consumption, making it ideal for analyzing both flat and hierarchical designs. GloryEye provides a one-stop timing Signoff platform, combining STA, SI analysis, power analysis and comprehensive constraint management for seamless timing closure.

Core Features&Product Highlights

Supports both NLDM and CCS timing models with multiple process node coverage
Provides comprehensive timing constraint and design rule verification
Implements advanced process variation analysis (GOCV/AOCV/POCV/LVF) across nodes
Delivers full-chip and block-level timing analysis precision
Maintains hierarchical vs. flatten analysis consistency
Offers traditional and advanced latch timing analysis modes
Performs CCSN-based SI analysis for crosstalk and noise accuracy
Enables low-power design verification across all voltage domains
Supports both Path-based and Complete PBA modes to reduce pessimism
Generates comprehensive STA and SI reports with metric visualization
Utilizes multi-threading for optimized runtime and memory efficiency
3DIC Static Timing Analysis Support : Enables parasitic parameter extraction and back-annotation for 3DIC structures. Features a process corner reduction algorithm to significantly reduce Signoff runtime while leveraging an advanced hierarchical Signoff flow to support large-scale chip timing closure.
Parallel Distributed Multi-Scenario Execution: Supports concurrent analysis of multiple modes and process corners, multi-voltage designs, and full-chip or block-level timing verification.
Ultra-Large-Scale Chip Analysis: Optimized for static timing analysis of chips with 200M+ instances, featuring multi-task and multi-threaded processing capabilities.

Workflow

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Products

GloryEXChip-Level RC Parasitic Extraction Tool GloryEX3DDevice-Level High-Efficiency Parasitic Field Solver GloryPolarisHigh-Precision 3D Modeling Tool for Parasitic Parameters GloryBoltFull-Chip Power Grid/Signal Line EM/IR Signoff Tool PhyBoltMulti-Physics Domain-Coupling Analysis for 3D IC and Chiplet GloryWattFull-chip Power Signoff Tool GloryEyeFull-Chip Static Timing Analysis Tool

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