Phlexing specializes in the Signoff field of chip design including SoC, ASIC, Memory, Custom and AMS chips, developing tools for analyzing power integrity, signal integrity, parasitic parameter extraction, power, reliability, static timing analysis, substrate noise, physical domain analysis, process design optimization, etc. With our edge in software algorithm and IC design, we strive to enrich our solutions and to lead the EDA industry in the post-Moore era.
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GloryEX
Chip-Level RC Parasitic Extraction Tool
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GloryEX3D
Device-Level High-Efficiency Parasitic Field Solver
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GloryPolaris
High-Precision 3D Modeling Tool for Parasitic Parameters
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GloryBolt
Full-Chip Power Grid/Signal Line EM/IR Signoff Tool
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PhyBolt
Multi-Physics Domain-Coupling Analysis for 3D IC and Chiplet
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GloryEye
Full-Chip Static Timing Analysis Tool
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