CN
GloryEX

High Accuracy Full-Chip Parasitic Extraction Solution

Introduction
GloryEX offers high-performance parasitic RC extraction with Signoff accuracy for IC designs. It builds physical effects modeling at advanced process nodes. It models deep-submicron complex structures’ physical effects using an ultra-high-precision 3D solver. GloryEX pioneers a unified 3D and 2.5D capacitance modeling technique with great speed and accuracy, and it also offers innovative compact 2.5D pattern matching technology to extract parasitics of ultra-large-scale system. GloryEX integrates 3D and 2.5D parasitic extraction modeling in parallel to provide transistor and gate level extraction with end-to-end runtime parameters, and it supports taking Signoff specifications from design users. The built-in 3D field solver, as a golden reference tool, extracts the highest accuracy of parasitics in the EDA industry. GloryEX develops its own integrated 2.5D and 3D tech file which is compatible with other mainstream tech files.
Highlights
  • Support designs for SoC, ASIC, Memory, Custom, AMS etc. 

  • 3D extraction mode and 2.5D fast extraction mode with high accuracy

  • Support high accuracy extraction of BEOL, MEOL and FEOL at advanced process nodes

  • Offer technology modeling of complex geometric structures and different physical effects. Support technology modeling of complex device structures and parasitic parameters in advanced nodes

  • High-accuracy 3D technology modeling of special structures for Foundry Golden standard

  • Offer 3D device structure display interface that enables developers to check modeling data and 3D configuration. Accurate characterization of conductor and dielectric parameters

  • Capable of multi-core parallel processing, domain partitioning, and hierarchical extraction; support rapid extraction of full-chip parameters in large-scale design

  • Offer large-scale and high-performance extraction at transistor-level and gate-level    

  • Provide precise 3D capacitance solver and accurate characterization of IP library in critical nets. Significant net-list compression for faster simulation and shorter run-time


Demonstration

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