Advanced-Process PDK Development
Empowering Advanced Process from R&D to Mass Production with Silicon-Data Accuracy
As process nodes cross the 3nm, GAA structures replace FinFET as the mainstream, and device 3D complexity rises exponentially. Even minute shifts in process parameters — such as fin height and gate pitch — erode timing margins and power budgets through the amplifying effects of parasitic capacitance and resistance. The accuracy of PEX (Parasitic Extraction) PDK parasitic modeling and EMIR rule check becomes decisive factors in the successful deployment of a new process. Using Silicon-Data-level modeling accuracy as its benchmark, Phlexing delivers a complete PDK development solution spanning PEX development, EMIR rule check, and tape-out preparation.
Core Highlights
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Silicon-Data-Level Accuracy Benchmark
Based on the FDM (Finite Difference Method), it builds a high-fidelity 3D process model using foundry measured silicon data as the benchmark, serving as the Golden standard for Rule Deck extractor accuracy calibration and eliminating systematic deviation. -
Three-Tier Precision Synergy
From Golden modeling to device-level field solving and finally full-chip rule verification, it covers the entire PDK parasitic development lifecycle end to end. -
Multi-Corner Parallel Verification
Equipped with MCPE (Multi-Corner Parallel Extraction), it covers all RC corners in a single pass, improving RC extraction efficiency by over 35%. -
DTCO Toolchain Support
Built on RC parasitic extraction, it provides unified data support across process R&D, PDK development, and design verification, accelerating the process iteration cycle.
Key Features
Applications
FinFET/GAA Advanced-Process PDK Development
A complete toolchain from device modeling to Rule Deck verification, covering 14nm and below process nodes.
Foundry PEX Accuracy Verification & Certification
Golden-standard accuracy comparison ensures Rule Deck consistency with silicon data, supporting PDK release.
Fabless PDK Adaptation & Optimization
Optimizes parasitic parameter configuration for specific design requirements, completing PDK accuracy confirmation and signoff preparation.
FinFET/GAA Advanced-Process PDK Development
A complete toolchain from device modeling to Rule Deck verification, covering 14nm and below process nodes.
Foundry PEX Accuracy Verification & Certification
Golden-standard accuracy comparison ensures Rule Deck consistency with silicon data, supporting PDK release.
Fabless PDK Adaptation & Optimization
Optimizes parasitic parameter configuration for specific design requirements, completing PDK accuracy confirmation and signoff preparation.