3DIC Multi-Die Electrical Signoff
Native 3DIC-Aware Full-Flow Electrical Signoff Solution
Accurate modeling of 3DIC vertical interconnect structures (e.g., TSV/Hybrid Bonding/Micro Bump), the power-thermal-timing multiphysics coupling induced by multi-die stacking, and signoff convergence across process corners and multi-mode scenarios constitute the three technical barriers that 3DIC electrical signoff must overcome. Conventional 2D toolchains lack native 3D awareness. Built on multi-die RC parasitic extraction as the foundation, Phlexing leverages its τ-Aware tool framework, to deliver a native 3DIC electrical signoff solution covering the full flow of timing, power integrity, and power-thermal coupling.
Core Highlights
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Native 3D-Aware Architecture
Rather than retrofitting a conventional 2D tool, it supports any Face-to-Face, Face-to-Back, and Back-to-Back stacking combinations, hundreds of millions of Hybrid Bonding connections. -
Multi-Process Data Fusion
The GTF (Glory Tech File) unified fusion mechanism enables seamless integration across foundry CapTable databases and compatibility with every foundry's 3D bonding data format. -
Early EMIR Signoff-Level Analysis
Based on a self-developed high-accuracy EMIR simulation solver, EMIR is rapidly assessed at the architecture stage; TSV placement, PG density, and misaligned power delivery are evaluated under zero-layout conditions. -
Unified Signoff Data Foundation
A unified SPEF/DSPF data language shares the RC parasitic parameter source, with progressive accuracy refinement from early fast-assessment mode to signoff mode, eliminating cross-tool data conversion loss.
Key Features
Applications
GPU/AI High-Performance Computing 3D-Stacked Chips
3D WoW integration of compute dies and memory dies, with cross-die timing and power-integrity signoff.
HBM High-Bandwidth Memory Stacking Chips
Vertical stacking of HBM/multi-layer DRAM dies; parasitic extraction and EMIR simulation for high-density TSV interconnects.
Multi-Process-Node, Multi-Fab Heterogeneous SoC
3D integration of dies at different process nodes and from different foundries, with GTF fusion and multi-foundry data collaboration.
GPU/AI High-Performance Computing 3D-Stacked Chips
3D WoW integration of compute dies and memory dies, with cross-die timing and power-integrity signoff.
HBM High-Bandwidth Memory Stacking Chips
Vertical stacking of HBM/multi-layer DRAM dies; parasitic extraction and EMIR simulation for high-density TSV interconnects.
Multi-Process-Node, Multi-Fab Heterogeneous SoC
3D integration of dies at different process nodes and from different foundries, with GTF fusion and multi-foundry data collaboration.
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